The present invention relates generally to the field of memory devices and, in particular, to a circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
Electronic systems typically store data during operation in a memory device. In recent years, the dynamic random access memory (DRAM) has become a popular data storage device for such systems. Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) in a large number of cells. The data is stored in a cell as a charge on a capacitor located within the cell. Typically, a high logic level is approximately equal to the power supply voltage and a low logic level is approximately equal to ground.
The cells of a conventional DRAM are arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes a word line that interconnects cells on the row with a common control signal. Similarly, each column includes a bit line that is coupled to at most one cell in each row. Thus, the word and bit lines can be controlled so as to individually access each cell of the array.
A memory array is typically implemented as an integrated circuit on a semiconductor substrate in one of a number of conventional layouts. One such layout is referred to as an xe2x80x9copen digit linexe2x80x9d architecture. In this architecture, the array is divided into at least two separate parts or xe2x80x9csub-arrays.xe2x80x9d Each sub-array includes a number of rows and columns of memory cells. Each memory cell in a row is coupled to a common word line and each transistor in a column is coupled to a common bit line. Each bit line in the first sub-array is paired with a bit line in the second sub-array so as to feed into a common sense amplifier. The sense amplifier detects and amplifies differences in voltage on a pair of bit lines as described in more detail below.
To read data out of a cell, the capacitor of a cell is accessed by selecting the word line associated with the cell. A complementary bit line that is paired with the bit line for the selected cell is equilibrated with the voltage on the bit line for the selected cell. The equilibration voltage is typically midway between the high and low logic levels. Thus, conventionally, the bit lines are equilibrated to one-half of the power supply voltage, Vcc/2. When the word line is activated for the selected cell, the capacitor of the selected cell discharges the stored voltage onto the bit line, thus changing the voltage on the bit line.
The sense amplifier detects and amplifies the difference in voltage on the pair of bit lines. The sense amplifier typically includes two main components: an n-sense amplifier and a p-sense amplifier. The n-sense amplifier includes a cross-coupled pair of n-channel transistors that drive the low bit line to ground. The p-sense amplifier includes a cross-coupled pair of p-channel transistors and is used to drive the high bit line to the power supply voltage.
An input/output device for the array, typically an n-channel transistor, passes the voltage on the bit line for the selected cell to an input/output line for communication to, for example, a processor of a computer or other electronic system associated with the DRAM. In a write operation, data is passed from the input(output lines to the bit lines by the input/output device of the army for storage on the capacitor in the selected cell.
Each of the components of a memory device are conventionally formed as part of an integrated circuit on a xe2x80x9cchipxe2x80x9d or wafer of semiconductor material. One of the limiting factors in increasing the capacity of a memory device is the amount of surface area of chip used to form each memory cell. In the industry terminology, the surface area required for a memory cell is characterized in terms of the minimum feature size, xe2x80x9cF,xe2x80x9d that is obtainable by the lithography technology used to form the memory cell. Conventionally, the memory cell is laid out with a transistor that includes first and second source/drain regions separated by a body or gate region that are disposed horizontally along a surface of the chip. When isolation between adjacent transistors is considered, the surface area required for such a transistor is generally 8F2 or 6F2.
Some researchers have proposed using a vertical transistor in the memory cell in order to reduce the surface area of the chip required for the cell. Each of these proposed memory cells, although smaller in size from conventional cells, fails to provide adequate operational characteristics when compared to more conventional structures. For example, U.S. Pat. No. 4,673,962 (the ""962 Patent) issued to Texas Instruments on Jun. 16, 1997. The ""962 Patent discloses the use of a thin poly-silicon field effect transistor (FET) in a memory cell. The poly-silicon FET is formed along a sidewall of a trench which runs vertically into a substrate. At a minimum, the poly-silicon FET includes a junction between poly-silicon channel (58) and the bit line (20) as shown in FIG. 3 of the ""962 Patent. Unfortunately, this junction is prone to charge leakage and thus the poly-silicon FET may have inadequate operational qualities to control the charge on the storage capacitor. Other known disadvantages of such thin film poly-silicon devices may also hamper the operation of the proposed cell.
Other researchers have proposed use of a xe2x80x9csurrounding gate transistorxe2x80x9d in which a gate or word line completely surrounds a vertical transistor. See, e.g., Impact of a Vertical "PHgr"-shape transistor (V"PHgr"T) Cellfor 1 Gbit DRAM and Beyond, IEEE Trans. On Elec. Devices, Vol 42, No. 12, December, 1995, pp. 2117-2123. Unfortunately, these devices suffer from problems with access speed due to high gate capacitance caused by the increased surface area of the gate which slows down the rise time of the word lines. Other vertical transistor cells include a contact between the pass transistor and a poly-silicon plate in the trench Such vertical transistor cells are difficult to implement due to the contact and should produce a low yield.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for realizable memory cell that uses less surface area than conventional memory cells.
The above mentioned problems with memory cells and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A memory cell is described which includes a vertical transistor with a trench plate trench capacitor and a body contact.
In particular, one embodiment of the present invention provides a memory cell. The memory cell includes an access transistor. The access transistor is formed in a pillar of single crystal semiconductor material. The transistor has first and second source/drain regions and a body region that are vertically aligned. The memory cell also includes a body contact that is coupled to the body region. A gate of the transistor is disposed on a side of the pillar that is opposite from the body contact. A trench capacitor is also included. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide. An insulator layer separates the access transistor and the trench capacitor from an underlying layer of semiconductor material.
In another embodiment, a memory device is provided. The memory device includes an array of memory cells. Each cell includes a vertical access transistor formed of a semiconductor pillar that extends outwardly from an insulator layer on a substrate. The access transistor has body and first and second source/drain regions, a gate disposed adjacent to a side of the pillar adjacent to the body region, and a trench capacitor. The first plate of the trench capacitor is integral with the first source/drain region and a second plate of the capacitor is disposed adjacent to the first plate. A number of bit lines are each selectively coupled to a number of the memory cells at the second source/drain region of the access transistor so as to form columns of memory cells. A number of word lines are also provided. Each word line is disposed orthogonally to the bit lines in a trench between rows of the memory cells for addressing gates of the access transistors of the memory cells that are adjacent to the word line. A number of body lines is also provided. Each body line is disposed in a trench between rows of memory cells so as to contact the body regions of access transistors on a side of the trench opposite the word line in the trench. Further the memory device includes a row decoder that is coupled to the word lines and body lines and a column decoder that is coupled to the bit lines so as to selectively access the cells of the array.
In another embodiment, a memory array is provided. The memory array includes an array of memory cells. Each memory cell includes an access transistor. The access transistor has body and first and second source/drain regions that are vertically formed outwardly from an insulator layer on a substrate in a single crystalline semiconductor pillar and a gate that is disposed adjacent to a side of the transistor. The second source/drain region includes an upper semiconductor surface. A number of word lines are included that interconnect gates of selected access transistors so as to form a number of rows of memory cells. A number of body address lines also interconnect body regions of selected access transistors in the rows of memory cells. A number of first isolation trenches separate adjacent rows of memory cells. Each isolation trench houses a word line and a body address line. A number of second isolation trenches are also provided. Each second isolation trench is substantially orthogonal to the first isolation trenches and interposed between adjacent memory cells so as to form a number of columns of the array.
In another embodiment, a method of fabricating a memory array is provided. A number of access transistors are formed. Each access transistor is formed in a pillar of semiconductor material that extends outwardly from a substrate. The access transistor includes a first source/drain region, a body region and a second source/drain region formed vertically thereupon. A trench capacitor, for each access transistor is also formed. A first plate of the trench capacitor is integral with the first source/drain region of the access transistor. A number of word lines interconnect the gates of a number of access transistors to form a row of the array. The word lines are disposed in a number of trenches that separate adjacent rows of access transistors. A number of body address lines that interconnect body regions of access transistors along the rows of the array are also formed. A number of bit lines that interconnect second source/drain regions of selected access transistors are formed so as to form a number of columns of the array.